In recent years, owing to advancement in semiconductor process technology, the minimum processing size is getting smaller and smaller. As a result, the number of transistors mounted in one chip increases, and SoC (System On a Chip) in which the prime functions of a computer are embedded in one chip becomes generalized. SoC integrates functional blocks, such as a micro-processor, an interface controller, a multimedia digital signal processor, a memory, etc. to one chip. By advancing such integration, an area necessary for implementation can be reduced and cost can be also markedly cut down, compared with a system formed by plural chips with an equivalent function. On the other hand, There arises a problem of increased power consumption of SoC in which a high level of integration is advanced. The increase of the power consumption leads to the increase in the heat production of a chip, and to the decrease in the reliability of the chip. In a portable device, the increase of the power consumption reduces a battery operating time. The increase of the power consumption is mainly attributable to the increased number of transistors integrated in a chip, the increased leakage current of a transistor accompanying miniaturization, and the increased operating frequency.
The power consumption can be classified into two kinds, a DC power and an AC power. The DC power originates in leakage current, and is consumed even in the state where the circuit is not operating, as long as the power supply voltage is applied. On the other hand, the AC power is a charge and discharge power of a transistor, and is consumed as operating power while the circuit is operating. In order to reduce the power consumption, it is important to reduce both DC power and AC power. In the following, however, paying attention to the DC power, the reduction technique proposed so far is explained.
SoC is a collective entity of power domains divided for every function. When looking at the operating state of SoC in a certain moment, all the circuits are not operating. This is because only the power domain necessary for the execution of application should be operating. Therefore, by cutting off the power supply to a power domain which is not used, the leakage current of the power domain can be brought to naught. This technique is described by Document 1 (Japanese patent laid-open No. 2003-218682), for example.
On the other hand, another technique of reducing the leakage current without performing power cut-off is also proposed. In the technique, the leakage current is reduced by setting the input value of a combination logic to a certain value compulsorily. This technique sets up the input value of a combination logic using a scan chain so that the leakage current may be reduced. This technique utilizes the fact that the leakage current of a chip changes depending on the value of a signal inputted into an input terminal of the combination logic. Taking an example of an AND gate of two inputs, the flowing leakage current differs depending on an input vector (00, 10, 01, 11). Namely, if it is possible to set up, directly in a combination logic, an input vector with which the leakage current becomes low in the time of sleep, etc., the DC power, i.e., the leakage current, can be reduced.
On the other hand, the direct control of a flip-flop output value of a sequential circuit, used as the input value of the combination logic, is difficult. Therefore, a multiplexer is added to the data input terminal of the flip-flop, and a path (scan chain) which couples flip-flops in series is formed apart from the usual path. The direct control of a value of the flip-flop is enabled by switching the data input source of the flip-flop to the normal path or to the scan chain path by a scan control signal. Namely, the input vector of the combination logic which exists in the normal path is set up using this scan chain, accordingly the leakage current is reduced. Although a scan chain is usually a path which is added for the sake of the design for testability, the scan chain is used here for leakage current reduction. This technique is described by Document 2 (Japanese patent laid-open No. 2006-220433), Document 3 (Japanese patent laid-open No. 2005-210009), and Document 4 (Japanese patent laid-open No. 2005-086215).